The present invention relates to a circuit arrangement for gating out pulses and/or pulse gaps whose duration is shorter than a given test period t.sub.p from a sequence of digital pulses present at the input end.
Circuit arrangements of the type described in the introduction are known. These circuit arrangements operate basically in analogue fashion with monostable multivibrators or integrators. In circuit arrangements having monostable multivibrators the test period t.sub.p is governed by the latter' triggering period .tau., whereas in circuits featuring integrators the test period t.sub.p is determined by the rise time to a given trigger-threshold voltage U.sub.O. In both cases the test period t.sub.p is determined by the time constant of the RC elements. If no special circuitry provisions are made, monostable multivibrators and integrators generally require a recovery time within which they are not available for re-use and which is also basically determined in terms of length by the time constant of the RC elements. On account of the resistance and capacitance tolerances always present in the RC elements, the circuit arrangements have the disadvantage that the test period cannot be prescribed with arbitrary accuracy. Also on account of the relatively long recovery time, uncontrollable adulterations of pulse lengths can occur which act as interferences in the output signal. A further disadvantage of these circuit arrangements is that the test period can only be varied by changes in the RC elements. Circuit arrangements having variable test periods are therefore not suitable for full integration, whereas in the case of circuits having a fixed test period the latter cannot be accurately determined. In addition, the test period is limited by the magnitude of the capacitance which can be technologically established on an integrated circuit. Another disadvantage in these circuit arrangements results from the temperature dependence of the RC elements and the threshold voltages.